As a configuration of a conventional solid-state imaging device, for example, in Kazuya Yonemoto's “Basic and application of CCD/CMOS image sensor,” CQ Publishing Co., Ltd., pp. 119 to 120 and 194 to 198 published issued on Aug. 10, 2003 “(hereinafter referred to as “Document 1”), a configuration of a solid-state imaging device including a column circuit for removing noise in pixels such as reset noise (KTC noise) for each column of pixels arranged in a two-dimensional matrix is disclosed. This column circuit removes a noise component included in an optical signal by performing a correlated double sampling (CDS) process of taking a difference between an optical signal photoelectrically converted by a pixel and a reset signal when the pixel is reset.
FIG. 14 is a circuit diagram showing a schematic configuration of a conventional solid-state imaging device including a column circuit. In FIG. 14, a configuration of a conventional solid-state imaging device 900 including a plurality of pixels 911 arranged in a two-dimensional matrix, a plurality of column circuits 950 corresponding to each column of the pixels 911, and an output amplifier 990 configured to amplify an optical signal after noise removal output from each column circuit 950 and output the amplified signal is shown. The column circuit 950 includes sampling switches 951, clamp capacitors 952, clamp switches 953, sampling capacitors 954, column output amplifiers 955, and column selection switches 956.
In the solid-state imaging device 900, optical signals and reset signals from the pixels 911 arranged in the same row are output to the corresponding column circuits 950.
Each of the column circuits 950 holds an optical signal after noise removal by taking the difference between the optical signal and the reset signal according to the configuration of the sampling switch 951, the clamp capacitor 952, the clamp switch 953, and the sampling capacitor 954. Thereafter, the column circuits 950 sequentially output optical signals after noise removal to the output amplifier 990 via the column output amplifiers 955 and the column selection switches 956 in accordance with selection of a column. Thereby, the output amplifier 990 amplifies the optical signals after the noise removal and sequentially outputs the amplified optical signals as final output signals (optical signals) output from the solid-state imaging device 900.
Meanwhile, although a noise component such as reset noise in each pixel can be removed in the solid-state imaging device 900 having the configuration shown in FIG. 14, other fixed pattern noise (FPN) also occurs and image quality will deteriorate. This fixed pattern noise is caused by a difference in characteristics between the column circuits 950 connected to the columns of the pixels 911 in the solid-state imaging device 900 having the configuration shown in FIG. 14, more specifically, a difference (variation) in characteristics between the column output amplifiers 955 provided in the column circuits 950.
Thus, Document 1 also discloses a solid-state imaging device with a configuration including an output circuit configured to output a signal of a level according to a difference between a signal level of a held optical signal and a signal level of a held reset signal as an output signal after each of the optical signal output from the pixel and the reset signal is temporarily held or sampled in the column circuit. However, in the solid-state imaging device with this configuration, it is not possible to completely remove fixed pattern noise due to variations in column circuits because sampling circuits provided in the column circuit (a sampling circuit for holding or sampling the optical signal and a sampling circuit for holding or sampling the reset signal) are controlled by different transistors.
Therefore, a solid-state imaging device having a configuration in which fixed pattern noise caused by the column circuit is removed by further sampling and holding the optical signal after noise removal output by the column circuit and the reset signal when the column circuit is reset can be conceived. In the solid-state imaging device with this configuration, a correlated double sampling circuit for sampling and holding each of the optical signal output from the column circuit and the reset signal and performing the correlated double sampling process is provided at a position of a stage previous to the output amplifier. A configuration in which the correlated double sampling circuit is provided at the position of the stage previous to the output amplifier has been applied to the conventional solid-state imaging device configured without a column circuit.
FIG. 15 is a circuit diagram showing a schematic configuration of a conventional solid-state imaging device including the correlated double sampling circuit in a stage previous to an output amplifier. In FIG. 15, an example of a configuration of a conventional solid-state imaging device 910 provided with a correlated double sampling (CDS) circuit 1000 configured to perform the correlated double sampling process by sampling and holding an optical signal and a reset signal after noise removal output from the column circuit 950 at a position previous to the output amplifier 990 provided in the conventional solid-state imaging device 900 shown in FIG. 14 is shown. The CDS circuit 1000 includes three sample-hold circuits (sample-hold circuits 1001 to 1003) and a differential amplifier 1004.
In the solid-state imaging device 910, column circuits 950 arranged in columns are sequentially selected, and final output signals (optical signals) corresponding to pixels 911 arranged in the columns are sequentially output. At this time, the CDS circuit 1000 samples and holds the reset signal of the column circuit 950 and the optical signal after the noise removal input from the column circuit 950 of the selected column via a horizontal signal line 960, and sequentially outputs a difference signal CDS-Out obtained by taking a difference between the sampled and held reset signal and the sampled and held optical signal after the noise removal to the output amplifier 990 as the optical signal after the noise removal output by the column circuit 950 of the selected column.
More specifically, in the CDS circuit 1000, the sample-hold circuit 1001 first holds (samples) the optical signal after the noise removal output by the column circuit 950 of a selected column in accordance with a sample-hold signal SHD. Thereafter, in the CDS circuit 1000, the sample-hold circuit 1003 holds (samples) the reset signal of the column circuit 950 of the selected column in accordance with a sample-hold signal SHP, and the sample-hold circuit 1002 holds (samples) the optical signal after the noise removal held in the sample-hold circuit 1001 again by moving the optical signal in accordance with the sample-hold signal SHP. In the CDS circuit 1000, the differential amplifier 1004 outputs the difference signal CDS-Out obtained by taking a difference between the optical signal after the noise removal held in the sample-hold circuit 1002 and the reset signal held in the sample-hold circuit 1003 to the output amplifier 990. Thereby, the output amplifier 990 amplifies the difference signal CDS-Out output from the CDS circuit 1000, i.e., the optical signal from which noise components in the pixel 911 and the column circuit 950 are removed, and outputs the amplified difference signal CDS-Out (optical signal) as a final output signal (optical signal) output by the solid-state imaging device 910.
Here, a driving timing in the solid-state imaging device 910 will be described. FIG. 16 is a timing chart showing an example of a driving timing in the conventional solid-state imaging device 910 including the correlated double sampling circuit (the CDS circuit 1000) in a stage previous to the output amplifier 990. In FIG. 16, an example of the driving timing when three columns are sequentially selected and the final output signal (optical signal) corresponding to the pixel 911 of each column is output is shown. More specifically, in FIG. 16, timings of a column selection control signal CSEL(1) for selecting the pixel 911 of a first column, a column selection control signal CSEL(2) for selecting the pixel 911 of a second column, a column selection control signal CSEL(3) for selecting the pixel 911 of a third column, the sample-hold signal SHD for controlling the holding (sampling) of the optical signal after noise removal, and the sample-hold signal SHP for controlling the holding (sampling) of the reset signal are shown. Also, in FIG. 16, a signal level of the difference signal CDS-Out from which noise is removed from a signal level of the horizontal signal line 960 by which each column circuit 950 outputs a signal is shown.
As shown in FIG. 16, in the CDS circuit 1000, during the period in which the column circuit 950 is selected by the column selection control signal CSEL(1), the column selection control signal CSEL(2), or the column selection control signal CSEL(3), the optical signal after noise removal output by the selected column circuit 950 is held (sampled) in the sample-hold circuit 1001 in accordance with the sample-hold signal SHD. Thereafter, in the CDS circuit 1000, the reset signal of the selected column circuit 950 is held (sampled) in the sample-hold circuit 1003 in accordance with the sample-hold signal SHP. Also, in the CDS circuit 1000, the optical signal after the noise removal held in the sample-hold circuit 1001 in accordance with the sample-hold signal SHP is moved to the sample-hold circuit 1002 and held (sampled). Thereby, in the CDS circuit 1000, the differential amplifier 1004 outputs the difference signal CDS-Out obtained by taking a difference between the optical signal after the noise removal held in the sample-hold circuit 1002 and the reset signal held in the sample-hold circuit 1003. At this time, the fixed pattern noise due to a variation in the column circuit 950 is removed from the difference signal CDS-Out.